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RAM Sizes and Speeds
Now that we have discussed the various
types of RAM and their function, it is appropriate to discuss the various
sizes and speeds that RAM can be found in.
One of the more difficult things to do in the world of
PC hardware is to Identify how much memory is on
a particular module without some kind of label, decal,
or screen-printed text on the module itself. Most modern memory
modules however will have a series of numbers printed
on the chips themselves. It commonly follows a DxW-S format,
which is explained below.
- D: The first letter specifies the
bit depth, measured in millions of bits.
Each number represents how many megabits of memory
cells. Be very clear that we are dealing with megabits
and not megabytes.
- W: The next letter specifies the
bit width of each cell in the module. A
30-pin SIMM has an 8-bit width, 72-pin
SIMMs have a 32-bit width, and DIMMs have a 64-bit
width. ECC RAM variations have 9, 36, or 72
bit width respectively. To determine the size
of the module that you're looking at, you would take DxW /
8.
This will yield the size of the module in megabytes.
For example, if we had 168-pin DIMM and it was labeled
as being an 8x64 module, this would make it a 64MB
(8 x 64 / 8) DIMM module. It is important to note that when
calculating parity or ECC modules, the extra
bits used for parity information are not counted.
For example in a 9-bit module only 8-bits are used in the calculation.
- S: The S specifies the speed of
the module nanoseconds. This be defines how fast
a module can read or write to the memory
bus. Refer to the table below to see the different depths, widths,
and speeds of various SIMM and DIMM memory modules.
SPEED-O-RAM
The speed of a RAM modules access time is measured in nanoseconds. |
Table 11: Summary of RAM Package Specifications by Size
Size in MB
|
30-pin SIMM Non-Parity
|
30-Pin SIMM Parity
|
72-Pin SIMM Non-Parity
|
72-Pin SIMM Parity
|
168-Pin DIMM No-Parity
|
168-Pin DIMM Parity
|
1 MB
|
1x8
|
1x9
|
256kx32
|
256kx36
|
--
|
--
|
2 MB
|
2x8
|
2x9
|
512kx32
|
512kx36
|
--
|
--
|
4 MB
|
4x8
|
4x9
|
1x32
|
1x36
|
--
|
--
|
8 MB
|
8x8
|
8x9
|
2x32
|
2x36
|
1x64
|
1x72
|
16 MB
|
16x8
|
16x9
|
4x32
|
4x36
|
2x64
|
2x72
|
32 MB
|
--
|
--
|
8x32
|
8x36
|
4x64
|
4x72
|
64 MB
|
--
|
--
|
16x32
|
16x36
|
8x64
|
8x72
|
128 MB
|
--
|
--
|
32x32
|
32x36
|
16x64
|
16x72
|
256 MB
|
--
|
--
|
64x32
|
64x36
|
32x64
|
32x72
|
512 MB
|
--
|
--
|
128x32
|
128x32
|
64x64
|
64x72
|
![[spacer]](1p.gif) How Memory Accesses Occur
Accessing memory in a PC is a very detailed and complex operation. It is certainly not required knowledge for the A+ Core Exam. However, certain issues surrounding the process can affect system performance. |
Lets begin by explaining exactly
how memory is addressed by the system.
As you have learned, memory is organized
into banks. A bank of memory contains modules of memory. The modules
are made up of memory chips, which are in turn divided into cells. Each
cell contains a certain number of bits, which is expressed by the bit
width.
For example, a 16x32 module contains
16M (16,777,216) cells of 32 bits each. This yields a memory module
with a total capacity of 64 MB (67,108,864 bits). Referring back to
our packaging chart, this would be a 64MB 72-pin SIMM. If we used this
in a Pentium class system, we would need a matching SIMM to complete
a 128MB bank of memory (Still with me?).
Continuing with this example, using
binary math we would determine that the system would require a 24-bit
address bus to address the 16M cells (224 = 16,777,216).
However, memory cells are logically organized into a square
containing rows and columns. You can think of this like a spreadsheet.
If I wanted to access cell M12, I would find row 12, then move to column
M. The memory controller breaks accesses up the same way.
For example, our processor needs
to access cell 15,342,195 in our SIMM module. This would have a binary
equivalent of:
111010100001 101001110011
The memory controller takes the first
12-bits as the row address, then it uses the last 12-bits as the column
address. Using this method, the address bus need only be 12 bits wide
instead of 24 bits. This equals lower costs to the manufacturer.
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CertiGuide to A+ (Core Hardware) (http://www.CertiGuide.com/aplush/) on CertiGuide.com
Version 1.0 - Version Date: December 6, 2004
Adapted with permission from a work created by Tcat Houser.
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