CertiGuide to A+ (Core Hardware)  9  Chapter 0011:  System Memory       9  V  Checking For Errors

Parity RAM 1 False Parity Memory

The more advanced and reliable form of error detection and correction protocol in the memory system is Error Checking Correcting (or Error Checking Code, or Error Checking Circuit), also known as ECC. ECC became available in Pentium class systems, and is only available in systems that support ECC mode. The ECC protocol will detect single and multi-bit errors, and correct single bit errors automatically. It does this by a complex algorithm that requires 7 bits to protect 32 bits, or 8 bits to protect 64 bits.

ECC requires special circuitry that is encoded in the chipset of the motherboard. Most chipsets that support ECC also include a way to report corrected errors to the operating system. Therefore it is up to the operating system to support these reports. Windows NT and Linux both support these messages.

Is also important to note that ECC mode will cause a 2% to 3% slowdown in system performance as the memory controller will need to generate and work with this error detection and correction algorithm.

When detecting multi-bit errors, ECC mode will perform in a similar manner to that of parity RAM, in which the parity circuit will report a not-maskable interrupt (NMI) error and halt the processor. It does not however, do any correcting of multi-bit errors. It is important to note however, that multi-bit errors are about as common as being struck by lightning twice in the same day. The upside is that ECC's reporting features make troubleshooting hard memory errors and software bugs much easier.

Parity RAM 1 False Parity Memory